Implement AND Gate in Verilog

Objective

Design and verify a simple 2-input AND gate using Verilog.
The design should be tested using a testbench that applies all possible input combinations.

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Requirements

1. Create a Verilog module named and_gate with:

   • Two inputs: a, b
   • One output: y
   • Function: y = a & b

2. Write a testbench module to verify the AND gate:

   • Apply all 4 input combinations of a and b (00, 01, 10, 11).
   • Observe the output y for correctness.

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