Problem: Half Adder in Verilog

Introduction

A Half Adder is the simplest digital circuit that performs binary addition.
It takes two 1-bit inputs and produces two outputs:

• Sum → result of XOR operation
• Carry → result of AND operation

In this tutorial, we will describe how to design and test a Half Adder using RTL (Register Transfer Level) modeling in Verilog.

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Step 1: Understand the Logic

The Half Adder works with the following logic equations:

• Sum Equation:
  Sum = A ⊕ B

• Carry Equation:
  Carry = A · B

Truth Table

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Step 2: RTL Modeling Concept

In RTL style:

• Outputs are declared as reg because they are assigned inside an always block.
• The block always @(*) is used for combinational logic.
• Inside the block, we describe the equations for sum and carry.

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Step 3: Writing the Testbench

A testbench is used to apply all input combinations and observe the outputs.
It should include:

1. Declaration of input regs and output wires.
2. Instantiation of the Half Adder module.
3. An initial block where inputs are changed over time.
4. Simulation ending with $finish.

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Step 4: Simulation and Verification

1. Compile the design and testbench with your simulator (e.g., iverilog).
2. Run the simulation executable.
3. Open the waveform file (e.g., in GTKWave) to observe the signals.
4. Compare results with the truth table to confirm correctness.

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Common Mistakes to Avoid

• Forgetting to declare sum and carry as reg when using RTL modeling.
• Not using always @(*), which may cause incomplete sensitivity list issues.
• Confusing the XOR (^) with OR (|) operator when writing equations.

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