Problem: Implement Half Subtractor in Verilog (gate level)

Objective

A Half Subtractor is a combinational circuit that subtracts one 1-bit binary input (b) from another (a).
It produces two outputs:

• Difference (D) → result of subtraction
• Borrow (B) → indicates when a borrow is required

In this tutorial, you will design a half subtractor using Verilog and test it with all input combinations.

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Explanation (How it works)

The half subtractor handles subtraction of two bits only — it cannot handle borrow from a previous stage (that’s why it’s half).

• Difference Equation:
  D = a ⊕ b

• Borrow Equation:
  B = (~a) & b
  (Borrow is needed when a = 0 and b = 1.)

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Requirements

1. Create a Verilog module named half_subtractor with:
   • Inputs: a, b
   • Outputs: diff, borrow
2. Implement using the logic equations:
   • assign diff = a ^ b;
   • assign borrow = (~a) & b;
3. Write a testbench module to verify:
   • Apply all 4 input combinations (00, 01, 10, 11).
   • Observe difference and borrow.

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Expected Truth Table

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Test Plan (What to do)

1. Simulate testbench and inspect signals a, b, diff, borrow in waveforms.
2. Verify diff = a ⊕ b and borrow = (~a) & b for all inputs.
3. Ensure truth table matches simulation results.

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Common Pitfalls

• Forgetting to invert a in the borrow equation.
• Using a - b directly in Verilog (not recommended for logic design tutorials).
• Not testing all input cases.

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Extension (Challenge)

• Compare the circuit with a Full Adder and notice the symmetry between addition and subtraction.