Parameterized Delay Line

Problem Description

Implement a parameterized delay line that delays input data by one clock cycle. The module should be parameterized to support different data widths.

Module Interface

• Parameter:
  • WIDTH: Data width (default: 8)
• Inputs:
  • clk: Clock signal
  • reset: Reset signal (active high)
  • din: WIDTH-bit data input
• Output:
  • dout: WIDTH-bit delayed data output

Expected Behavior

• On reset: Both delay register and output are set to 0
• On each clock edge: din is stored in delay register, previous delay value goes to dout