4-bit Shift Register

Problem Description

Implement a 4-bit shift register that shifts data to the left on each clock cycle.

Module Interface

• Inputs:
  • clk: Clock signal
  • reset: Reset signal (active high)
  • in: 1-bit serial input
• Output:
  • out: 4-bit parallel output

Expected Behavior

• On reset: Clear all bits to 0
• On each clock edge: Shift left, new bit enters from right (LSB)
• out[3] = previous out[2], out[2] = previous out[1], out[1] = previous out[0], out[0] = in