4-bit Up Counter

Problem Description

Implement a 4-bit up counter that increments on each clock cycle.

Module Interface

• Inputs:
  • clk: Clock signal
  • reset: Reset signal (active high)
• Output:
  • count: 4-bit counter output

Expected Behavior

• On reset: count = 0
• On each clock edge: count = count + 1
• Counter wraps around from 15 to 0