Vector Array Logic

Implement a module that uses a vector array (4-bit elements) to store and retrieve values.

Module Interface

• Inputs:
  • clk: Clock signal
  • reset: Reset signal (active high)
  • addr: 2-bit address
• Output:
  • data_out: 4-bit data output

Expected Behavior

• On reset: Initialize array with values [0001, 0010, 0100, 1000]
• On each clock edge: Output the value at array[addr]